{"id":7761,"date":"2021-02-23T15:56:32","date_gmt":"2021-02-23T07:56:32","guid":{"rendered":"https:\/\/cde.nus.edu.sg\/ece\/?page_id=7761"},"modified":"2025-02-13T15:47:00","modified_gmt":"2025-02-13T07:47:00","slug":"signal-processing-and-vlsi-lab","status":"publish","type":"page","link":"https:\/\/cde.nus.edu.sg\/ece\/signal-processing-and-vlsi-lab\/","title":{"rendered":"Signal Processing and VLSI Lab"},"content":{"rendered":"\n

\n\t\tSignal Processing and VLSI Lab\n\t<\/h2>\n\t

Introduction:<\/h3>\nThe laboratory provides support to the research activities of integrated circuits & embedded systems. It also supports the department activities relevant to IC design, including teaching modules.\n

The research activities include:<\/p>\n

    \n
  1. Analog, mixed-signal, digital and RF integrated circuits with focus on securities, communication and biomedical applications,<\/li>\n
  2. design and VLSI implementation of high performance digital integrated circuit and systems,<\/li>\n
  3. reconfigurable computing and electronic design automation,<\/li>\n
  4. embedded system design,<\/li>\n
  5. sensors, MEMS, and integrated systems.<\/li>\n<\/ol>\nThe laboratory houses a network of Linux servers\/workstations, software tools, and various test equipment. The software tools include EDA tools, such as Cadence, Synopsys and Mentor Graphics tools and, etc. The equipment housed in the laboratory is the integrated circuit test equipment and the general-purpose test instruments, such as network analyser, parameter analyser, pulse generators, VCO\/PLL analyser, signal generators and dc power supplies and, etc.\n
    \n

    Staff:<\/h3>\n
    \n\n\n\n\n\n
    Academic Staff<\/th>\nSupport Staff<\/th>\n<\/tr>\n<\/thead>\n
    ALIOTO, MASSIMO BRUNO (Professor)<\/a>\n

    HENG CHUN HUAT (Associate Professor)<\/a><\/p>\nJang Moonhyung (Assistant Professor)<\/a><\/td>\n

    		TEO Seow Miang (Laboratory Officer)\nZHENG Huan Qun (Professional Officer)<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n

    CAD Support:<\/h3>\n

    Note: You may need to enter your NUS User-ID and Password to access some of the links below:<\/p>\n

    \n\n\n\n\n\n
    Information for Users<\/th>\nEDA Tools<\/th>\n<\/tr>\n<\/thead>\n
    Information for Account Users<\/a>\n

    Remote Access with Tunneling VNC Over SSH<\/a><\/p>\nRemote Access with Xming and Putty<\/a><\/td>\n

    		Cadence University Program<\/a>\n

    Cadence Tools<\/p>\n

    Siemens Tools<\/p>\nSynopsys Tools<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n <\/figure>\n

    \n\n\n\n\n\n
    IC Design Manuals<\/th>\n<\/tr>\n<\/thead>\n
    Simulation Manual with Cadence tools (ac, dc, transient and xf simulations)<\/a>new<\/sup>\n

    Analog IC Desing Manual with Cadence IC 6 and Cadence Verification Tools<\/a><\/p>\n

    LT Spice Manual for Digital Circuit Simulation<\/a><\/p>\n

    Analog IC Desing Manual with Cadence IC 6 and Mentor Graphics Calibre<\/a><\/p>\n

    ASIC Design Manual with CADENCE and SYNOPSYS Tools<\/a><\/p>\n

    IC Design Manual – Schematic & Simulation with MENTOR GRAPHICS Tools<\/a><\/p>\n

    LT Spice Tutorial for Analog Circuit Simulation<\/a><\/p>\n

    Mixed Signal Design Manual with CADENCE Tools<\/a><\/p>\nUsage Guide of DRC with Calibre<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n

    Useful Links:<\/h3>\n
    \n\n\n\n\n\n
    Foundries<\/th>\nEDA Tool Online Forums<\/th>\nCareer Information<\/th>\n<\/tr>\n<\/thead>\n
    ASIC – austriamicrosystems Support Information Center<\/a>\n

    GLOBALFOUNDRIES INC<\/a><\/p>\n

    MEMSCAP<\/a><\/p>\n

    MOSIS IC Service Home Page<\/a><\/p>\n

    STMicroelectronics<\/a><\/p>\n

    TSMC Semiconductor<\/a><\/p>\n

    United Microelectronics Corporation (UMC)<\/a><\/p>\nX-FAB Mixed-Signal Foundry Experts<\/a><\/td>\n

    		Cadence Technology Forums<\/a>\n

    Synopsys Blogs and Forums<\/a><\/p>\nSiemens Support Center<\/a><\/td>\n

    		Website – set up by EDB<\/a>\nCareer Central<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n

    Contact Us:<\/h3>\n
    \n\n\n\n\n\n
    Telephone<\/th>\nAddress<\/th>\nLocation<\/th>\n<\/tr>\n<\/thead>\n
    (65)66013404 \/ (65)65168890<\/td>\nSignal Processing and VLSI Lab
    \nDepartment of Electrical and Computer Engineering
    \nNational University of Singapore
    \n4 Engineering Dr 3, Singapore 117583<\/td>\n    		Staff & Research Scholars Room: E4 #08-27, 28, 29
    \nVLSI Measurement Room 1: E4 #08-26
    \nVLSI Measurement Room 2: E4 #08-25<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n\n","protected":false},"excerpt":{"rendered":"

    Signal Processing and VLSI Lab Introduction: The laboratory provides support to the research activities of integrated circuits & embedded systems. It also supports the department activities relevant to IC design, including teaching modules. The research activities include: Analog, mixed-signal, digital and RF integrated circuits with focus on securities, communication and biomedical applications, design and VLSI […]<\/p>\n","protected":false},"author":31,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"set","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""}},"footnotes":""},"class_list":["post-7761","page","type-page","status-publish","hentry"],"acf":[],"_links":{"self":[{"href":"https:\/\/cde.nus.edu.sg\/ece\/wp-json\/wp\/v2\/pages\/7761","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/cde.nus.edu.sg\/ece\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/cde.nus.edu.sg\/ece\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/cde.nus.edu.sg\/ece\/wp-json\/wp\/v2\/users\/31"}],"replies":[{"embeddable":true,"href":"https:\/\/cde.nus.edu.sg\/ece\/wp-json\/wp\/v2\/comments?post=7761"}],"version-history":[{"count":4,"href":"https:\/\/cde.nus.edu.sg\/ece\/wp-json\/wp\/v2\/pages\/7761\/revisions"}],"predecessor-version":[{"id":21113,"href":"https:\/\/cde.nus.edu.sg\/ece\/wp-json\/wp\/v2\/pages\/7761\/revisions\/21113"}],"wp:attachment":[{"href":"https:\/\/cde.nus.edu.sg\/ece\/wp-json\/wp\/v2\/media?parent=7761"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}