{"id":20454,"date":"2026-07-15T15:50:59","date_gmt":"2026-07-15T07:50:59","guid":{"rendered":"https:\/\/cde.nus.edu.sg\/mse\/?post_type=nus-news&#038;p=20454"},"modified":"2026-07-15T15:51:17","modified_gmt":"2026-07-15T07:51:17","slug":"nus-cde-applied-materials-researchers-develop-atom-thin-coating-for-smaller-chips","status":"publish","type":"nus-news","link":"https:\/\/cde.nus.edu.sg\/mse\/news\/nus-cde-applied-materials-researchers-develop-atom-thin-coating-for-smaller-chips\/","title":{"rendered":"NUS CDE\u2013Applied Materials researchers develop atom-thin coating for smaller chips"},"content":{"rendered":"<p>Researchers from NUS CDE and Applied Materials have developed an ultra-thin film that could enable smaller, faster and more reliable computer chips.<\/p>\n<figure id=\"attachment_20456\" aria-describedby=\"caption-attachment-20456\" style=\"width: 1920px\" class=\"wp-caption alignnone\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-20456 size-full\" src=\"https:\/\/cde.nus.edu.sg\/mse\/wp-content\/uploads\/sites\/4\/2026\/07\/SG-and-team.png.avif\" alt=\"\" width=\"1920\" height=\"1280\" srcset=\"https:\/\/cde.nus.edu.sg\/mse\/wp-content\/uploads\/sites\/4\/2026\/07\/SG-and-team.png.avif 1920w, https:\/\/cde.nus.edu.sg\/mse\/wp-content\/uploads\/sites\/4\/2026\/07\/SG-and-team.png-300x200.avif 300w, https:\/\/cde.nus.edu.sg\/mse\/wp-content\/uploads\/sites\/4\/2026\/07\/SG-and-team.png-1024x683.avif 1024w, https:\/\/cde.nus.edu.sg\/mse\/wp-content\/uploads\/sites\/4\/2026\/07\/SG-and-team.png-768x512.avif 768w, https:\/\/cde.nus.edu.sg\/mse\/wp-content\/uploads\/sites\/4\/2026\/07\/SG-and-team.png-1536x1024.avif 1536w\" sizes=\"auto, (max-width: 1920px) 100vw, 1920px\" \/><figcaption id=\"caption-attachment-20456\" class=\"wp-caption-text\">From right: Members of the research team from the Department of Materials Science and Engineering, Prof Silvija Grade\u010dak, Dr M Juvaid, Mr Chung Jing-Yang, and Dr Hippolyte Astier<\/figcaption><\/figure>\n<p>The global semiconductor market is approaching US$1 trillion in annual sales, driven by growing demand for faster computers, smarter AI systems and more powerful electronic devices. Singapore, which produces one in 10 of the world\u2019s chips, has a direct stake in sustaining that trajectory. For decades, advances in chip performance have relied on shrinking transistor size, pushing semiconductor technology ever closer to its physical limits. But a bottleneck is emerging at one of the most fundamental levels of chip architecture: the tiny wiring inside computer chips. While the copper wires connecting transistors are becoming smaller with each new generation, the protective layers around them cannot shrink as easily, making it harder to improve chip speed, efficiency and reliability.<\/p>\n<p>Copper wires inside chips need two protective coatings: a barrier to stop copper atoms from migrating into surrounding materials, which can cause short circuits and chip failure, and a liner to help copper adhere and form smooth, reliable connections. Today\u2019s standard coatings, made from tantalum-based materials, must be at least four nanometres thick to function. In the next generation of chips, these protective layers could take up as much as half of the wire\u2019s cross-section, sharply increasing electrical resistance and reducing chip speed and efficiency. A collaboration between the National University of Singapore (NUS) and <a href=\"https:\/\/www.appliedmaterials.com\/sg\/en.html\" target=\"_blank\" rel=\"noopener\">Applied Materials<\/a> has now resulted in a single material thin enough to preserve copper\u2019s share of the wire yet capable of performing both of these functions.<\/p>\n<p><iframe loading=\"lazy\" title=\"YouTube video player\" src=\"\/\/www.youtube.com\/embed\/_7aMAPUpeOI?si=tz_Z_TaeC26WmpRz\" width=\"560\" height=\"315\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\"><\/iframe><\/p>\n<p>Researchers at the Applied Materials\u2013NUS Advanced Materials Corporate Lab, working across the <a href=\"https:\/\/cde.nus.edu.sg\/mse\/\" target=\"_blank\" rel=\"noopener\">Department of Materials Science and Engineering<\/a> in the College of Design and Engineering at NUS (NUS CDE) and the Department of Chemistry at the NUS Faculty of Science, together with researchers from Applied Materials, developed a process for growing crystalline tungsten disulfide (WS<sub>2<\/sub>) films just 0.7 nanometres thick \u2014 roughly the width of a few atoms \u2014 on industry-standard 200-millimetre wafers. Published in <a href=\"https:\/\/www.nature.com\/articles\/s41928-026-01592-6\"><em>Nature Electronics<\/em><\/a> on 31 March 2026, the study shows that even an atomically thin WS\u2082 monolayer can serve as both barrier and liner, allowing chipmakers to keep shrinking circuits without sacrificing speed or reliability.<\/p>\n<p>\u201cImportantly, the process works at low temperatures and across full wafers, making it readily compatible with existing chip manufacturing lines\u201d, stated Dr M. Juvaid Mangattuchali, who had co-led the research with Dr Hippolyte Astier, both from the Department of Materials Science and Engineering.<\/p>\n<figure id=\"attachment_20459\" aria-describedby=\"caption-attachment-20459\" style=\"width: 1920px\" class=\"wp-caption alignnone\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-20459 size-full\" src=\"https:\/\/cde.nus.edu.sg\/mse\/wp-content\/uploads\/sites\/4\/2026\/07\/SG-and-team-microscopy.png-1.avif\" alt=\"\" width=\"1920\" height=\"1080\" srcset=\"https:\/\/cde.nus.edu.sg\/mse\/wp-content\/uploads\/sites\/4\/2026\/07\/SG-and-team-microscopy.png-1.avif 1920w, https:\/\/cde.nus.edu.sg\/mse\/wp-content\/uploads\/sites\/4\/2026\/07\/SG-and-team-microscopy.png-1-300x169.avif 300w, https:\/\/cde.nus.edu.sg\/mse\/wp-content\/uploads\/sites\/4\/2026\/07\/SG-and-team-microscopy.png-1-1024x576.avif 1024w, https:\/\/cde.nus.edu.sg\/mse\/wp-content\/uploads\/sites\/4\/2026\/07\/SG-and-team-microscopy.png-1-768x432.avif 768w, https:\/\/cde.nus.edu.sg\/mse\/wp-content\/uploads\/sites\/4\/2026\/07\/SG-and-team-microscopy.png-1-1536x864.avif 1536w\" sizes=\"auto, (max-width: 1920px) 100vw, 1920px\" \/><figcaption id=\"caption-attachment-20459\" class=\"wp-caption-text\">The team inspecting an electron microscopic image of the ultra-thin layer of tungsten disulfide.<\/figcaption><\/figure>\n<p><strong>One layer, two functions<\/strong><\/p>\n<p>The researchers first demonstrated that as a liner, the WS<sub>2<\/sub> coating helps copper form a smooth, continuous film rather than forming disconnected clusters \u2014 a problem that affects ultrathin copper deposited directly on a chip\u2019s insulating layer. With coating, the resistance dropped by more than a millionfold compared with uncoated surfaces. The single atomic layer also outperformed the conventional tantalum-based stack by roughly five times, despite being nearly 10 times thinner \u2014 0.7 nanometres vs approximately six nanometres for the industry standard.<\/p>\n<p>The thickness gap has direct implications for chip performance. In a future 20-nanometre-wide wire, the current industry coating would occupy 40 per cent of the wire\u2019s diameter. The WS<sub>2<\/sub> layer takes up just 7per cent, leaving substantially more room for copper to carry current.<\/p>\n<p>The team then investigated whether the same ultrathin WS<sub>2<\/sub> layer could also serve as a barrier to stop copper atoms from leaking into surrounding chip materials. Under prolonged heat stress, copper on uncoated surfaces reacted with the underlying silicon, forming large defective structures. With a single WS<sub>2<\/sub> layer in place, no reaction or intermixing occurred. Moreover, under electrical stress, the WS<sub>2<\/sub> barrier extended projected wire lifetimes by more than 10-fold compared with unprotected devices.<\/p>\n<p>\u201cThe key challenge was ensuring that a layer so thin could still function reliably as both a liner and a barrier. Conventional wisdom held that you needed two separate materials \u2014 one for the barrier, one for the liner \u2014 with a combined thickness of at least four nanometres. Showing that a single monolayer of WS<sub>2<\/sub> can do what that two-layer stack currently does opens the door to a fundamentally different approach to interconnect design,\u201d said Professor <a href=\"https:\/\/cde.nus.edu.sg\/mse\/staff\/gradecak-silvija\/\" target=\"_blank\" rel=\"noopener\">Silvija Grade\u010dak<\/a> from the NUS Department of Materials Science and Engineering, and Co-Director of the Corporate Lab.<\/p>\n<p>Computational modelling by researchers in NUS\u2019 Department of Chemistry revealed why the material\u2019s structure makes it particularly effective as a barrier. The WS<sub>2<\/sub> grown by this process is composed of many tiny crystalline grains, and in multilayer films those grains are randomly oriented from one layer to the next. Defects and grain boundaries therefore do not align across layers \u2014 much like offset joints in a brick wall \u2014 making it substantially harder for copper atoms to pass through.<\/p>\n<p>\u201cThe calculations showed us that the polycrystalline nature of these films, which might initially seem like a limitation compared with a perfect single crystal, is actually an asset. The random grain orientations between layers create a labyrinth that copper atoms struggle to traverse,\u201d said Professor Richard Wong from the NUS Department of Chemistry, who is also a Co-Director of the Corporate Lab. \u201cThis gives us a design principle, where we engineer the grain structure to optimise barrier performance instead of pursuing perfect crystallinity.\u201d<\/p>\n<p><strong>Designed for the production line<\/strong><\/p>\n<p>For any new material to enter chip manufacturing, it must meet strict production requirements. The team\u2019s growth process \u2014 thermal atomic layer deposition at 350 degrees Celsius, without plasma \u2014 satisfies all four key requirements for integration into existing chip fabrication lines: a temperature low enough to avoid damaging underlying chip layers; uniform coverage across an entire industry-standard wafer; precise thickness control down to a single atomic layer; and conformal coating of deep, narrow trenches (greater than 95 per cent coverage at depth-to-width ratios of 10 to 1). No previous method for growing two-dimensional materials had met all four simultaneously.<\/p>\n<p>\u201cThe resulting films are thinner than any barrier or liner target on the international semiconductor technology roadmap through to 2037, positioning the material not just for the next generation of chips but potentially for several generations beyond,\u201d said Dr Astier.<\/p>\n<p>\u201cMany promising materials are being explored, but the gap between a research demonstration and a process that can run in a production facility is substantial. By working through the Corporate Lab, we were able to test these films against the constraints that chipmakers actually face. Meeting these four requirements with a single continuous film makes this result relevant to the industry,\u201d added Dr John Sudijono, Director of Engineering at Applied Materials, and Co-Director of the Corporate Lab.<\/p>\n<p>Future directions include investigating the 2D interface at the microscopic level to understand how grain structure relates to long-term wire reliability, as well as exploring whether greater control over grain orientation could further improve performance. The study also demonstrates the viability of using the same low-temperature and industry-compatible growth approach to integrate ultrathin 2D materials into other components of future computer chips.<\/p>\n<p>&nbsp;<\/p>\n<p><span style=\"font-size: 10pt;\"><em>Article from College of Design and Engineering, NUS<\/em><\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Researchers from NUS CDE and Applied Materials have developed an ultra-thin film that could enable smaller, faster and more reliable computer chips. The global semiconductor market is approaching US$1 trillion in annual sales, driven by growing demand for faster computers, smarter AI systems and more powerful electronic devices. Singapore, which produces one in 10 of<\/p>\n","protected":false},"author":15,"featured_media":20456,"parent":0,"menu_order":0,"template":"","meta":{"_acf_changed":false,"rs_blank_template":"","rs_page_bg_color":"","slide_template_v7":"","site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","ast-disable-related-posts":"","theme-transparent-header-meta":"default","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"set","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"footnotes":""},"news_category":[36],"class_list":["post-20454","nus-news","type-nus-news","status-publish","has-post-thumbnail","hentry","news_category-news"],"acf":[],"_links":{"self":[{"href":"https:\/\/cde.nus.edu.sg\/mse\/wp-json\/wp\/v2\/news\/20454","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/cde.nus.edu.sg\/mse\/wp-json\/wp\/v2\/news"}],"about":[{"href":"https:\/\/cde.nus.edu.sg\/mse\/wp-json\/wp\/v2\/types\/nus-news"}],"author":[{"embeddable":true,"href":"https:\/\/cde.nus.edu.sg\/mse\/wp-json\/wp\/v2\/users\/15"}],"version-history":[{"count":3,"href":"https:\/\/cde.nus.edu.sg\/mse\/wp-json\/wp\/v2\/news\/20454\/revisions"}],"predecessor-version":[{"id":20460,"href":"https:\/\/cde.nus.edu.sg\/mse\/wp-json\/wp\/v2\/news\/20454\/revisions\/20460"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/cde.nus.edu.sg\/mse\/wp-json\/wp\/v2\/media\/20456"}],"wp:attachment":[{"href":"https:\/\/cde.nus.edu.sg\/mse\/wp-json\/wp\/v2\/media?parent=20454"}],"wp:term":[{"taxonomy":"news_category","embeddable":true,"href":"https:\/\/cde.nus.edu.sg\/mse\/wp-json\/wp\/v2\/news_category?post=20454"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}